Company: Micron Technology Inc
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Our history of giving back started in 1999 when we established the Micron Foundation and identified science, technology, engineering and math (STEM) education as a priority for Idaho students. Today, the Micron Foundation’s initiatives have become leading resources for educators and students in Idaho communities and beyond, and we donate millions of dollars to organizations and events identified by our local teams around the world.
Company Website: www.in.micron.com
Positions: Engineer – Standard Cell Design
Experience: 2-4 years
Job Location: Hyderabad
Salary: Best In Industry
Education: BE/ B.Tech/ ME/ M.Tech – Electrical/ Electronics/ Micro Electronics Engineering.
Job Description:
- As a Memory Analog and Standard cell Characterization Validation Engineer, you will work with a highly innovative and motivated design team using state of the art memory technologies to develop the most advanced DRAM and Emerging memory products.
- You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 10M transistors), ultra-high-speed designs, complex functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies.
- You will need to have the ability to work as a Memory Analog and Stdcell Characterization Validation Engineer, to verify and validate the Analog block circuitry and standard cells through the verification methodology and tools.
- You will work closely with Micron’s various design and verification teams all over the world to contribute to the success of the design projects by applying verification tools and techniques, providing verification status and summaries to specific designs as needed
Job Responsibilities:
- Design and Maintain standard cells for new products based on new technology.
- Characterize the performance of standard cells and optimize the standard cell design and layout.
- Characterization and modeling of Stdcell and specific Custom cells to provide timing/power model for verification.
- Quality Analysis of characterized liberty models in terms of Timing, Power and Functionality.
- Develop automation test bench/flow/tools to improve the work efficiency and help data analysis.
- Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
- Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products
Requirements:
- Good understanding of CMOS circuit design
- Good knowledge of CMOS device physics and layout
- Experience in SiliconSmart, Liberate, Liberate_LV, PT and Cadence Virtuoso preferred
- Familiar with analog/digital simulation tools, i.e. HSPICE, HSIM, VerilogHDL, FINESIM, SimVision
- Experience in Analog block design and verification preferred
- Experience in Standard Cell design and verification preferred
- Experience in using Skill, TCL, Perl, Python to do test bench automation and data analysis preferred
- Previous work experience in DRAM memory related fields is a plus
- Must possess good communication skills and ability to work well in a team
Application Link: Click Here